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2.5GHz, +20dBm Power Amplifier IC
in UCSP Package
Table 1. Control Inputs
DIGITAL CONTROL INPUTS
OUTPUT POWER AND SUPPLY CURRENT
SHDN
0
1
1
1
1
D1
0
0
0
1
1
D0
0
0
1
0
1
POWER LEVEL
PA OFF-
P1
P2
P3
P4
P IN
(dBm)
3
3
3
3
3
P OUT
(dBm)
-22
3
8
12
19
I CC (mA)
<1μA
65
68
75
105
four levels (magnitudes) of precisely controlled currents
to the VGA, depending on power control digital inputs
D0 and D1. Each current level presents a different
power level to the final amplifier stage, therefore con-
trolling the output power.
The digital power control circuit of the PA greatly sim-
plifies control of the output power. The two digital bits
D0 and D1 control the output power in four steps with
approximately a 6dB/step. The PA is optimized to pro-
vide power control steps within a 2dB/step to 8.6dB/
step over the full temperature range and V CC and RF
input power variations. Table 1 shows the D0 and D1
digital control states, the corresponding nominal output
power, and the typical current consumption of the IC.
The bias circuit provides separate bias voltages and
currents to the amplifier stages. An internal lowpass RC
filter isolates the bias circuit from being corrupted by
the RF signals. The bias circuit is optimized to minimize
output power variations due to the variations in temper-
ature, V CC , and RF power input. The bias circuit design
also ensures the stability of the PA when connected to
high VSWR loads over all power levels. A digital low at
the SHDN port turns the amplifier down with a current
consumption of less than 1μA.
The MAX2240 integrates all the RF matching compo-
nents on-chip, except for the output stage match. The
internal input match enables the RF input with 50 Ω
impedance to be directly connected to the RFIN port
through a 50 Ω transmission line.
The MAX2240 PA requires an external match at the
RFOUT port to optimize the amplifier for output power
and efficiency. For an optimum match at 2.45GHz, the
load impedance at the RFOUT port is approximately
15 Ω + j18 Ω (Figure 1). There are numerous ways of
transforming 50 Ω to the optimum impedance. The out-
put matching in the typical operating circuit is imple-
mented using a series transmission line of 75 Ω and
electrical length of 26°, and an open-ended shunt stub
of 65 Ω and 41° in length. The shunt stub also reduces
the second harmonic at the output.
Applications Information
The MAX2240 power amplifier requires a relatively
small number of external components. These compo-
nents are small, low-cost surface-mount passive ele-
ments. The capacitors are all 0402 multilayer ceramic
chip capacitors. These capacitors possess excellent
high-frequency properties and are cost effective. The
Typical Application Circuit is shown on page 1.
The inductor is a Q (>25) 0603 chip inductor. All trans-
mission lines are simple microstrip structures printed
on the PC board.
Power-Supply Considerations
The MAX2240 is designed to operate from a single, posi-
tive supply voltage (V CC ). Three pins are fed by the sup-
ply voltage: BIAS, V CC , and RFOUT. Each supply
voltage connection requires a separate RF bypass
capacitor for proper operation. Use a 0.1μF bypass
capacitor to filter the supply at the common V CC node
(see Typical Application Circuit).
BIAS requires a 220pF capacitor to ground. Locate one
end of the capacitor as close as possible to BIAS and
the other end of the capacitor near GND1 with several
vias to the ground plane.
V CC powers the amplifier 1st stage output. A 1.2nH
inductor in series with V CC and the V CC bypass capaci-
tor is needed for optimal output power and efficiency.
An 18pF bypass capacitor to ground is required at the
supply end of the 1.2nH inductor.
RFOUT is connected to the power supply through a
choke inductor (through transmission line section T1).
Select a choke with a self-resonant frequency at or
slightly below 2.4GHz. A 220pF bypass capacitor is
needed at the supply voltage end of the inductor.
6
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